1. Field of the Invention
The present invention generally relates to semiconductor devices operating in synchronization with a clock signal, and particularly relates to a semiconductor device in which electric power consumption can be reduced by controlling a clock signal.
2. Description of the Related Art
In semiconductor devices such as processors, the frequency of a clock signal is lowered or suspended for the purpose of reducing power consumption during a period in which high-speed processing is not required. Namely, the frequency of a clock signal is switched in a step-like manner as necessary (hereinafter called a “clock gear”), or the supply of the clock signal is suspended with respect to module blocks that do not need to be operating (hereinafter called a “power-down mode”).
The clock gear is generally implemented by supplying a synchronizing signal for mask purposes that corresponds to the fastest clock signal used in the processor and by reducing the number of clock pulses by use of a gated clock buffer. Alternatively, the clock gear is implemented by dividing the frequency of a clock signal by a frequency divider. The power-down mode is generally implemented by masking the supply of a clock signal to all or part of the modules in the processor during a period in which their operations are not necessary. Such clock control is generally attended to by a clock control unit of the processor operating based on settings provided to chip terminal pins and software control provided by programs.
When a shift of the clock gear or a shift to the power-down mode is to be made in a configuration having an on-chip bus or an internal peripheral bus provided via a bus bridge inside the processor, a predetermined procedure must be performed based on software control. Namely, when a shift of the clock gear or a shift to the power-down mode is to be made, software-based operations need to be performed as preparation for such a shift in compliance with the predetermined protocols (operation specifications) relating to bus transfer and the like.
If the clock gear is changed during data transfer trough a bus (especially, during an instruction fetch) without performing such a required procedure, there is a risk of causing the processor to suffer a hang-up state due to the failure to fetch an instruction. Further, when a store instruction is carried out as a released operation handed over to a module that is connected to an internal peripheral bus via a bus bridge, for example, a write operation continues to be performed on the internal peripheral bus even after transfer on the on-chip bus is completed. If the clock gear is shifted without waiting for the store operation to be completed, there is a risk that the storing of data is not properly carried out. Further, when an SDRAM (synchronous dynamic random memory) controller is provided on a chip, for example, data of the SDRAM will be destroyed if the clock of the SDRAM controller is suspended without making the SDRAM shift into a self-refresh mode.
In order to avoid the problems as described above, a software program for performing a predetermined procedure necessary for a clock-gear shift or a transition to the power-down mode must be created in advance. If this predetermined procedure is not perfect up to minute details, however, an unpredictable hang-up or the like may occur.
Especially when a clock control program needs to be created for processors having an on-chip bus, a bus bridge, a chip-external bus (i.e., a bus that is connected to an SDRAM, SRAM, ROM, companion chip, or the like) operating based on complicated transfer protocols, the control procedure needs to take into account various conditions. It is thus difficult to eliminate all the risks of causing a hang-up state or data transfer errors through human errors.
Accordingly, there is a need for a semiconductor device that is provided with a hardware mechanism for eliminating the risk of causing a hang-up state at the time of a clock-gear shift or a transition to the power-down mode.